The invention relates in general to the structure and fabrication of integrated circuits and more particularly to an integrated circuit providing effective protection of selected circuit components, such as transistors and ferroelectric materials, against diffusion of oxygen and hydrogen.
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See U.S. Pat. No. 5,046,043 issued Sep. 3, 1991 to Miller et al. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Lead-containing ABO3-type ferroelectric oxides such as PZT (lead zirconium titanate) and PLZT (lead lanthanum zirconium titanate) have been studied for practical use in integrated circuits. Layered superlattice material oxides have also been studied for use in integrated circuits. See U.S. Pat. No. 5,434,102 issued Jul. 18, 1995 to Watanabe et al. Layered superlattice materials exhibit characteristics in ferroelectric memories that generally are superior to those of PZT and PLZT compounds. Integrated circuit devices containing ferroelectric elements are currently being manufactured. Nevertheless, problems associated with oxygen degradation and hydrogen degradation during the manufacturing process hinders the economical production in commercial quantities of ferroelectric memories and other IC devices using either the ABO3-type oxides or the layered superlattice material compounds with the desired electronic characteristics.
A typical memory in an integrated circuit contains a semiconductor substrate and a metal-oxide semiconductor field-effect transistor (MOSFET) electrically connected to a capacitor device. Layered superlattice materials and other dielectric capacitor materials currently in use and development comprise metal oxides. In conventional fabrication methods, crystallization of the metal oxides to produce desired electronic properties requires heat treatments in oxygen-containing gas at elevated temperatures. The heating in the presence of oxygen is typically performed at a temperature in a range of 500xc2x0 C. to 900xc2x0 C. for 60 minutes to three hours. As a result of the presence of reactive oxygen at elevated temperatures, numerous defects, such as dangling bonds, are generated in the single crystal structure of the semiconductor silicon substrate, leading to deterioration in the electronic characteristics of the MOSFET. Good ferroelectric properties have been achieved in the prior art using process heating temperatures at about 700xc2x0 C. to crystallize layered superlattice material. See U.S. Pat. No. 5,508,226 issued Apr. 16, 1996 to Ito et al. Nevertheless, the long exposure times for up to several hours in oxygen, even at the somewhat reduced temperature ranges, results in oxygen damage to the semiconductor substrate and other elements of a CMOS circuit.
After completion of the integrated circuit, the presence of oxides may still cause problems because oxygen atoms from a thin film of metal oxide capacitor dielectric, for example, from ferroelectric layered superlattice material, tend to diffuse through the various materials contained in the integrated circuit and combine with atoms in the integrated circuit substrate and in semiconductor layers forming undesired oxides. The resulting oxides interfere with the function of the integrated circuit; for example, they may act as dielectrics in the semiconducting regions, thereby forming virtual capacitors.
Diffusion of atoms from the underlying semiconductor substrate and other circuit layers into the ferroelectric metal oxide (or other dielectric metal oxide) is also a problem; for example, silicon from a silicon substrate and from polycrystalline silicon contact layers is known to diffuse into layered superlattice material and degrade its ferroelectric properties. For relatively low-density applications, the ferroelectric memory capacitor is placed on the side of the underlying CMOS circuit, and this may reduce somewhat the problem of undesirable diffusion of atoms between circuit elements. Nevertheless, as the market demand and the technological ability to manufacture high-density circuits increase, the distance between circuit elements decreases, and the problem of molecular and atomic diffusion between elements becomes more acute. To achieve high circuit density by reducing circuit area, the capacitor of a memory cell is placed virtually on top of the switch element, typically a field-effect transistor (xe2x80x9cMOSFETxe2x80x9d), and the switch and bottom electrode of the capacitor are electrically connected by an electrically conductive plug. To inhibit undesired oxygen diffusion, a barrier layer is sometimes disposed under the ferroelectric or other dielectric oxide, between the capacitor""s bottom electrode and the underlying layers. The barrier layer must inhibit the diffusion of oxygen and other chemical species that may cause problems; it must also be electrically conductive, to enable electrical connection between the capacitor and the switch. Such barrier layers are typically limited in size to cover only the surface area of an integrated circuit substrate located approximately directly below the capacitor.
To restore the silicon properties of the MOSFET/CMOS, the manufacturing process typically includes a forming-gas, or hydrogen, annealing (xe2x80x9cFGAxe2x80x9d) process, in which defects such as dangling bonds-are eliminated by utilizing the reducing property of hydrogen. Various techniques have been developed to effect the hydrogen annealing, such as H2-gas heat treatment in ambient conditions. Conventionally, hydrogen treatments are conducted between 350xc2x0 C. and 550xc2x0 C., typically around 400xc2x0 C. to 450xc2x0 C. for a time period of about 30 minutes. In addition, the CMOS/MOSFET manufacturing process requires other fabrication processes that expose the integrated circuit to hydrogen, often at elevated temperatures, such as hydrogen-rich plasma CVD processes for depositing metals and dielectrics, growth of silicon dioxide from silane or TEOS sources, and etching processes using hydrogen and hydrogen plasma. During processes that involve hydrogen, the hydrogen diffuses through the top electrode and the side of the capacitor to the thin film of metal-oxide capacitor dielectric (e.g., ferroelectric layered superlattice material) and reduces the oxides contained in the dielectric material. The absorbed hydrogen also metallizes the surface of the dielectric thin film by reducing metal oxides. The adhesivity of the dielectric thin film to the upper electrode is lowered by the chemical change taking place at the interface. Alternatively, the upper electrode is pushed up by the oxygen gas, water, and other products of the oxidation-reduction reactions taking place. As a result of these effects, the electronic properties of the capacitor are degraded, and peeling is likely to take place at the interface between the top electrode and the dielectric thin film. In addition, hydrogen also can reach the lower electrode, leading to internal stresses that cause the capacitor to peel off its substrate. These problems are acute in ferroelectric memories containing layered superlattice material compounds because these metal oxide compounds are particularly complex and prone to degradation by hydrogen-reduction. After a forming-gas anneal (FGA), the remanent polarization of the ferroelectrics typically is very low and no longer suitable for storing information. Also, an increase in leakage currents results.
Several methods have been reported in the art to inhibit or reverse, hydrogen degradation of desired electronic properties in ferroelectric oxide materials. Oxygen annealing at high temperature (800xc2x0 C.) for about one hour results in virtually complete recovery of the ferroelectric properties degraded by hydrogen treatments. However, the high-temperature oxygen anneal itself may generate defects in silicon crystalline structure, and it may-offset somewhat the positive effects of any prior forming-gas anneal on the CMOS characteristics. Special metallization layers and diffusion barrier layers have also been examined to minimize the effects of hydrogen during high-energy processes and forming-gas annealing processes. The metallization schemes typically involve the use of materials that are prone to oxidation in an oxygen-containing environment at temperatures above 400xc2x0 C. Aluminum, the primary metallization material, has a low melting point and cannot tolerate temperatures above 450xc2x0 C. Thus, oxygen annealing of an integrated circuit substrate to repair prior hydrogen degradation is often not practically possible. Encapsulation of metal-oxide capacitor dielectric with hydrogen-diffusion barriers has been proposed in the prior art; nevertheless, it is often not completely effective, and it typically requires complex process schemes including depositing and removing the hydrogen barrier material.
Structures and methods in accordance with the invention provide integrated circuits that avoid the degradation of electronic properties resulting from undesired diffusion of oxygen and hydrogen within an integrated circuit, especially within ferroelectric memory cells, but which do not add substantial changes to conventional CMOS processing or introduce complicated process schemes.
In one aspect, an embodiment in accordance with the invention provides an integrated circuit comprising a switch, a capacitor, and a nonconductive oxygen barrier located between the switch and the capacitor. In another aspect, the oxygen barrier comprises strontium tantalate. In still another aspect, the oxygen barrier further comprises silicon nitride. Both strontium tantalate and silicon nitride, alone or together, function as oxygen barriers, as well as hydrogen barriers.
In another aspect, the capacitor comprises a bottom electrode having a bottom-electrode side edge, and at least a portion of the oxygen barrier is located on the bottom-electrode side edge.
In one aspect, an embodiment in accordance with the invention comprises a conductive diffusion barrier comprising a conductive-barrier side edge, wherein the bottom electrode is located on the conductive diffusion barrier, and wherein at least a portion of the nonconductive oxygen barrier is located on the conductive-barrier side edge. Typically, a first insulator layer is located between the switch and the capacitor, and the conductive diffusion barrier is located on a portion of the insulator layer, and a portion of the oxygen barrier is located on the insulator layer.
In another aspect, the first insulator layer comprises a moat region, the moat region being defined partially by a moat sidewall and a moat bottom. In another aspect, the moat region is substantially coplanar with the bottom electrode and the conductive diffusion barrier. In another aspect, a portion of the nonconductive oxygen barrier is disposed on the moat bottom, and a portion of the nonconductive oxygen barrier is disposed on the moat sidewall.
In another aspect, the first insulator layer comprises an over-etched portion aligned with the conductive-barrier side edge, wherein the bottom-electrode side edge, the conductive-barrier side edge, and the over-etched portion define a moat sidewall, and at least a portion of the oxygen barrier layer is located on the bottom-electrode side edge, the conductive-barrier side edge, and the over-etched portion.
In another aspect, the conductive diffusion barrier and the nonconductive oxygen barrier together substantially completely cover the switch and together form a substantially continuous diffusion barrier between the capacitor and the switch.
In another aspect, an integrated circuit in accordance with the invention further comprises a nonconductive hydrogen barrier layer, the nonconductive hydrogen barrier layer substantially completely covering the capacitor and the switch. Preferably, the nonconductive hydrogen barrier layer comprises strontium tantalate. Preferably, the nonconductive hydrogen barrier layer further comprises silicon nitride.
In another aspect, the capacitor comprises a top electrode, and a portion of the nonconductive hydrogen barrier layer is located on the top electrode. Preferably, the capacitor comprises a top plate-line electrode, and a portion of the nonconductive hydrogen barrier layer is located on the plate-line electrode. In another aspect, an integrated circuit in accordance with the invention further comprises an electrical connection to the top plate-line electrode and the electrical connection is located remotely from the capacitor. In another aspect, the top electrode comprises a top-electrode side edge, and a portion of the nonconductive hydrogen barrier layer is located on the top-electrode side edge. In still another aspect, the capacitor comprises a capacitor dielectric film comprising a capacitor-dielectric side edge, and a portion of the nonconductive hydrogen barrier layer is located on the capacitor-dielectric side edge. Preferably, the conductive barrier layer comprises titanium aluminum nitride. In another aspect, the nonconductive hydrogen barrier layer substantially completely covers the capacitor and the switch. In still another aspect, an integrated circuit in accordance with the invention further comprises a non-memory portion, and the nonconductive hydrogen barrier layer does not cover the non-memory portion. Preferably, the nonconductive hydrogen barrier layer comprises strontium tantalate. Preferably, the nonconductive hydrogen barrier layer further comprises silicon nitride.
In another aspect, the capacitor comprises a thin film of ferroelectric layered superlattice material. Preferably, the thin film comprises ferroelectric layered superlattice material selected from the group consisting of strontium bismuth tantalate and strontium bismuth tantalum niobate. In still another aspect, the thin film has a thickness not exceeding 90 nm.
In one aspect, an embodiment of an integrated circuit in accordance with the invention comprises an element sensitive to degradation by oxygen and a nonconductive oxygen barrier layer comprising strontium tantalate located to protect the element. In another aspect, the oxygen barrier layer further comprises silicon nitride. In still another aspect, an integrated circuit in accordance with the invention further comprises an electrically conductive diffusion barrier located proximate to the oxygen barrier layer, and the conductive diffusion barrier and the oxygen barrier together form a substantially continuous diffusion barrier to protect the element.
In one aspect, a method of fabricating a memory cell comprises providing a substrate, which substrate contains a switch, a first insulator layer covering the switch, and a conductive plug, wherein the bottom end of the conductive plug is in electrical connection with the switch, and then forming a conductive diffusion barrier layer and a bottom electrode layer on the substrate.
A method further comprises removing a portion of the bottom electrode layer, of the conductive diffusion barrier layer, and of the insulator layer, thereby forming a bottom electrode, a conductive diffusion barrier, and an over-etched portion of the first insulator layer. In another aspect, removing-the portion of the insulator layer forms the over-etched portion of the insulator layer and a moat space adjacent to the conductive diffusion barrier and the bottom electrode.
In one aspect, a method further comprises forming a nonconductive oxygen barrier layer on the substrate. In another aspect, forming the oxygen barrier layer comprises depositing a portion of the oxygen barrier layer on a side edge of the bottom electrode. In another aspect, forming the oxygen barrier layer comprises depositing a portion of the oxygen barrier layer on a side edge of the conductive diffusion barrier. In still another aspect, forming the oxygen barrier layer comprises depositing a portion of the oxygen barrier layer on the over-etched portion of the moat sidewall. Preferably, forming the oxygen barrier layer comprises depositing a portion of the oxygen barrier layer on the bottom-electrode side edge, on the conductive-barrier side edge, and on the over-etched portion of the moat sidewall. In still another aspect, forming the oxygen barrier layer comprises depositing a portion of the nonconductive oxygen barrier layer on the first insulator layer. In another aspect, forming the oxygen barrier layer comprises depositing a portion of the oxygen barrier layer on the moat bottom. In still another aspect, forming the oxygen barrier layer comprises depositing the oxygen barrier layer such that the oxygen barrier and the conductive diffusion barrier together substantially completely cover the switch. In still another aspect, forming the oxygen barrier layer comprises forming the oxygen barrier layer proximate to the conductive diffusion barrier such that the oxygen barrier layer and the conductive diffusion barrier together constitute a substantially continuous diffusion barrier between the bottom electrode and the switch. Preferably, forming the oxygen barrier layer comprises depositing strontium tantalate. Preferably, forming the oxygen barrier layer also comprises depositing silicon nitride.
In another aspect, a method in accordance with the invention further comprises forming a capacitor dielectric layer and a top electrode layer on the substrate, forming a memory capacitor on the substrate, and thereafter depositing a nonconductive hydrogen barrier layer on the substrate, such that the hydrogen barrier layer substantially completely covers the memory capacitor and the switch. Preferably, depositing a nonconductive hydrogen barrier layer comprises depositing strontium tantalate. Preferably, depositing a nonconductive hydrogen barrier layer further comprises depositing silicon nitride.
In another aspect, forming a memory capacitor comprises removing a portion of the top electrode layer to form a top electrode, and depositing a nonconductive hydrogen barrier layer comprises depositing a portion of the nonconductive hydrogen barrier layer on the top electrode. In another aspect, forming a memory capacitor comprises removing a portion of the top electrode layer to form a top plate-line electrode, and depositing a nonconductive hydrogen barrier layer comprises depositing a portion of the nonconductive hydrogen barrier layer on the plate-line electrode. In still another aspect, forming a memory capacitor includes forming a top plate-line electrode having a top-electrode side edge, and depositing a nonconductive hydrogen barrier layer includes depositing a portion of the nonconductive hydrogen barrier layer on the top-electrode side edge.
In another aspect, a method in accordance with the invention comprises removing a portion of the capacitor dielectric layer to form a capacitor dielectric film having a capacitor-dielectric side edge, and depositing a nonconductive hydrogen barrier layer comprises depositing a portion of the nonconductive hydrogen barrier layer on the capacitor-dielectric side edge. In still another aspect, a method further includes removing a non-memory portion of the nonconductive hydrogen barrier layer from the substrate.
In another aspect, forming of the dielectric layer comprises depositing metal oxide precursor material for forming ferroelectric layered superlattice material. Preferably, forming the dielectric layer comprises forming a layered superlattice material selected from the group consisting of strontium bismuth tantalate and strontium bismuth tantalum niobate. Preferably, forming the dielectric layer includes heating the precursor material using RTP at a temperature in a range of about from 400xc2x0 C. to 800xc2x0 C. for a total duration of less than 30 minutes. More preferably, the total duration comprises less than 15 minutes. Even more preferably, the total duration comprises less than 5 minutes.